This application relates to the operation of re-programmable non-volatile memory systems such as semiconductor flash memory which record data using charge stored in charge storage elements of memory cells and to methods of operating such memory systems.
Many non-volatile memories are formed along a surface of a substrate (e.g. silicon substrate) as two-dimensional (2D), or planar, memories. Other non-volatile memories are three-dimensional (3D) memories that are monolithically formed in one or more physical levels of memory cells having active areas disposed above a substrate.
In a non-volatile memory, such as 3D NAND flash memory, data may be rapidly written into one of more blocks of memory cells (sometimes herein called SLC blocks) configured to store data using Single Level Cell (SLC) formatting (with one bit of data stored in each memory cell) when the data is first received by the memory device. Subsequently, the data may be copied or folded into a smaller number of memory cells in one or more blocks of memory cells (sometimes herein called MLC blocks) configured to store data using Multilevel Cell (MLC) formatting, with more than one bit of data stored in each memory cell. When this coping is performed within a single chip, or single memory device, the copying process is sometimes called an on-chip copy (OCC) process. While OCC improves the density of data stored in non-volatile memory, and enables high speed initial writing of the data to the memory device, OCC processes have been found to require significant chip resources for computing parity information for the data being folded into MLC blocks. In addition, parity information produced by OCC processes is typically stored in concentrated clusters of memory locations in the MLC blocks, resulting in the memory locations with parity information being read more frequently than if the data and corresponding parity information had been stored in SLC blocks, which in turn makes the parity information particularly vulnerable to a problem known as read-disturb.